The present invention relates generally to field of integrated circuit (IC) design. More specifically, the present invention is directed to a method and apparatus for sizing and insertion of decoupling capacitance.
High-speed digital integrated circuits (ICs) require a stable reference voltage, regardless of the input current required. However, spike currents generated during switching can cause Vcc and ground (GND) voltage level to fluctuate, causing ringing in the output waveform or a delay in response speed. The switching noise is caused by changes in current through various parasitic inductances. The simultaneous switching of I/O drivers and internal circuits can increase the voltage drop on the power supply. This power supply noise not only will introduce additional signal delay, but also may cause false switching of logic gates. Decoupling capacitors are used to reduce the impedance between power and ground, minimizing the effects of current spikes and board noise on the IC, keeping power supply within specification, and providing signal integrity.
For low-frequency power drop problems, it may be adequate to use only the off-chip decoupling capacitors. However, for high-frequency power drop problems, the on-chip decoupling capacitor is more effective due to its proximity to the switching activities. A problem with having on-chip decoupling capacitance to control the power noise is the size of the decoupling capacitors. The size of the decoupling capacitors can consume a significant part of die size, ranging generally from 3% to 15% of the die size.
One existing method of sizing decoupling capacitance uses a maximum-frequency analysis. Another method of sizing decoupling capacitance uses a worst-case pre-allocation technique where allocation is based on a percentage of layout area in a specific layout window. The percentage of the layout area and the layout window are given as design guidelines. The design guidelines are determined based on the study of the power noise budget and power supply network topologies on chip and on package. For example, the design guideline specifies that within 200 xcexcm layout window, 10-20% area should be used for the decoupling capacitance. Generally, these methods will result in a conservative estimate of the area reserved for decoupling capacitance.
According to one aspect of the invention, a method for allocating decoupling capacitance in a power grid is provided. The power grid is evaluated to identify noisy nodes. For each noisy node that violates voltage thresholds, a decoupling capacitor is inserted. The power grid is re-evaluated to determine the power nodes that still violate the voltage thresholds. The size of the decoupling capacitor at each noisy node is incremented until the corresponding power node is brought to within the voltage thresholds.